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Это любопытно @VLSI HUB
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Это любопытно, но оказывается есть вариант ко-симуляции простых аналогово-цифровых схем (spice+verilog) в QSPICE. Внутри блоков X1 и X2 слинкованы verilog-файлы сигма-дельта АЦП и ЦАП из репо:
https://github.com/davemuscle/sigma_delta_converters

@vlsihub

VLSI HUB
Это любопытно, но оказывается есть вариант ко-симуляции простых аналогово-цифровых схем (spice+verilog) в QSPICE. Внутри блоков X1 и X2 слинкованы verilog-файлы сигма-дельта АЦП и ЦАП из репо:
https://github.com/davemuscle/sigma_delta_converters

@vlsihub
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hottg.com/vlsihub/664
2.16K viewsDmitry Murzinov, 


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Это любопытно

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