Good solution to replace direct instantiating vendor-dependent clock buffer BUFG like that:
BUFG bufg_inst (instread to use the HDL-pragma like that (verilog):
.I(clkin),
.O(clk_pcie)
);
(* clock_buffer_type = "BUFG" *) input clk_pcie;Another BUFx type also aplicable for this pragma
#Xilinx #BUFG #primitives
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